In recent years, the demand for low power consumption has become stronger for mobile light-emitting display devices. A display which uses a Liquid Crystal Display Device, LCD, or self-light emitting device such as an organic EL display or electronic paper and the like are adopted as a display device for mobile purposes.
Among these, an organic EL display in particular does not require a back light and furthermore, since the drive voltage of a light emitting device is low, organic EL displays are attracting attention as a low power consumption and light emitting flat panel display device.
In addition, these light emitting display devices for mobile use are often attached with touch panels such as smartphones, tablets or PC's. In display devices attached with touch panels, by arranging a common electrode above a pixel region, a structure in which noise is shielded from the touch panel from a horizontal scanning signal and perpendicular scanning signal is usual.
However, in the above mentioned structure, since parasitic capacitance which occurs between a drive circuit arranged in a periphery region and a common electrode increases, there is a tendency for power consumption to increase with higher resolution and higher drive speeds. As a method for solving this problem, for example, a technology is proposed in Japanese Laid Open Patent 2003-288987 in which parasitic capacitance is reduced by reducing the film thickness of an interlayer insulation film above a lower layer wiring and reducing the thickness of an interlayer insulation film at an intersection point between a lower layer wiring and upper layer wiring.
As described above, it is necessary to reduce parasitic capacitance as much as possible in order to provide a light emitting display device with low power consumption. However, as in patent document 1 for example, in a technology which only reduces the thickness of an interlayer insulation film above a lower layer wiring, an interlayer insulation film pattern corresponding one to one to a lower layer wiring pattern becomes necessary. That is, because it is necessary to form an interlayer insulation film pattern which matches a lower layer wiring, the level of freedom in circuit design is remarkably reduced.